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FEATURES
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LTC6602 Dual Matched, High Frequency Bandpass/Lowpass Filters DESCRIPTION
The LTC(R)6602 is a dual, matched, programmable bandpass or lowpass filter and differential driver. The selectivity of the LTC6602, combined with its phase matching and dynamic range, make it ideal for filtering in RFID systems. With two degree phase matching between channels, the LTC6602 can be used in applications requiring highly matched filters, such as transceiver I and Q channels. Gain programmability, and the fully differential inputs and outputs, simplify implementation in most systems. Both channels of the LTC6602 consist of a programmable lowpass and highpass filter. For bandpass functionality, the lowpass filters are programmed for the upper cutoff frequency. For lowpass functionality, the highpass filters can be bypassed. The filter cutoff frequencies can be set with a guaranteed accuracy of 3% with the use of a single resistor. Alternatively, the filter cutoff frequencies can be controlled with an external clock. The LTC6602 operates on a single 2.7V to 3.6V supply and features a low power shutdown mode.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners..
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Matched Dual Filter/Driver, Ideal for RFID Readers Guaranteed Phase Matching to Within 2 Degrees Guaranteed Gain Matching to Within 0.2dB Configurable as Lowpass or Bandpass Programmable 5th Order Lowpass: 42kHz to 900kHz Programmable 4th Order Highpass: 4.2kHz to 90kHz Programmable Gain: 1x, 4x, 16x, 32x Simple Pin Programming or SPI Interface Low Noise: -145dBm/Hz (Input Referred) Low Distortion: -75dBc at 200kHz Differential, Rail-to-Rail Inputs and Outputs Input Range Extends from 0V to 5V Low Voltage Operation: 2.7V to 3.6V Shutdown Mode 4mm x 4mm QFN Package
APPLICATIONS
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Multiprotocol RFID Readers: EPC-GEN2, ISD and IPX IDEN, PHS, GSM Basestations Repeaters, Radio Links, and Modems Wireless Telemetry JTRS
TYPICAL APPLICATION
UHF RFID Reader Dual Baseband Filter and Dual ADC
3V 0.1F 0.1F 20 100 100pF V+IN +INA I INPUT Q INPUT 38.3k 0.1F -INA +INB -INB RBIAS VOCM MUTE MUTE INPUT FROM TRANSMITTER LTC6602 V+A V+D -OUTA +OUTA -OUTB +OUTB CLKIO SER CLKCNTL 100 100pF 100pF 100pF BIN- Q OUTPUT 100 2.2F BIN+ 14-BIT ADC I OUTPUT VCM LTC2297 100 100pF 100pF AIN- AIN+ 14-BIT ADC 10 0 GAIN (dB) -10 -20 -30 -40 -50 45kHz-300kHz BPF -60 1k 10k 100k 1M FREQUENCY (Hz) 10M
6602 TA01b
Gain vs Frequency
EXTERNAL CLOCK = 90MHz 15kHz-150kHz BPF 90kHz-900kHz BPF
GAIN0(D0) HPF0(SDO) GAIN1 GND GND HPF1(SDI) LPF0(SCLK) LPF1(CS) CS SCLK SDI SPI CONTROL INPUT /4 CLK IN
6602 TA01
CLOCK INPUT 24MHz TO 128MHz (COVERS THE TAG BACKSCATTER LINK FREQUENCY RANGE OF 40kHz to 640kHz OF THE CLASS 1 GENERATION 2 UHF RFID COMMUNICATION PROTOCOL)
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LTC6602 ABSOLUTE MAXIMUM RATINGS
(Note 1)
PIN CONFIGURATION
TOP VIEW GAIN0(D0) +OUTA 18 -OUTA 17 SER 25 16 V+D 15 CLKIO 14 GND 13 +OUTB 7 +INB 8 -INB 9 10 11 12 LPFO(SCLK) HPFO(SDO) HPF1(SDI) -OUTB GAIN1 MUTE +INA V+IN 1 V+A 2 VOCM 3 RBIAS 4 CLKCNTL 5 LPF1(CS) 6 -INA
V+IN to GND ................................................................6V V+A, V+D to GND .........................................................4V Filter Inputs to GND ....................... -0.3V to V+IN + 0.3V All Other Pins to GND.............. -0.3V to V+A, V+D + 0.3V Maximum Input Current .......................................10mA Output Short Circuit Duration........................... Indefinite Operating Temperature Range (Note 2) LTC6602CUF ........................................ -40C to 85C LTC6602IUF ......................................... -40C to 85C Specified Temperature Range (Note 3) LTC6602CUF ............................................ 0C to 70C LTC6602IUF ......................................... -40C to 85C Storage Temperature Range................... -65C to 150C
24 23 22 21 20 19
UF PACKAGE 24-LEAD (4mm x 4mm) PLASTIC QFN TJMAX = 150C, JA = 37C/W EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO THE PCB.
ORDER INFORMATION
LEAD FREE FINISH LTC6602CUF#PBF LTC6602IUF#PBF TAPE AND REEL LTC6602CUF#TRPBF LTC6602IUF#TRPBF PART MARKING* 6602 6602 PACKAGE DESCRIPTION 24-Lead (4mm x 4mm) Plastic QFN 24-Lead (4mm x 4mm) Plastic QFN SPECIFIED TEMPERATURE RANGE 0C to 70C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which app ly over the full operating temperature range, otherwise specifications are at TA = 25C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS Filter Gain Either Channel External Clock = 90MHz, Highpass Filter Cutoff = 45kHz, Gain = 0dB Lowpass Filter Cutoff = 300kHz, VIN = 3.6VP-P fIN = 22.5kHz fIN = 45kHz fIN = 150kHz fIN = 300kHz fIN = 900kHz Matching of Filter Gain External Clock = 90MHz, Highpass Filter Cutoff = 45kHz, Lowpass Filter Cutoff = 300kHz, VIN = 3.6VP-P fIN = 45kHz fIN = 150kHz fIN = 300kHz
ELECTRICAL CHARACTERISTICS
l l l l l
-1.8 0.1 -2.7
-32 -1.2 0.5 -2 -44
-30 -0.8 0.8 -1.2 -43
dB dB dB dB dB
l l l
0.2 0.2 0.2
dB dB dB
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LTC6602 ELECTRICAL CHARACTERISTICS
PARAMETER Filter Phase Either Channel CONDITIONS External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 45kHz, Lowpass Filter Cutoff = 300kHz fIN = 50kHz fIN = 250kHz External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 45kHz, Lowpass Filter Cutoff = 300kHz fIN = 50kHz fIN = 250kHz
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted.
MIN TYP MAX UNITS
l l
125 -134
130 -130
134 -126
deg deg
Matching of Filter Phase
l l
2 1.5
deg deg
Filter Gain Either Channel External Clock = 90MHz, Highpass Filter Cutoff = 15kHz, Gain = 0dB Lowpass Filter Cutoff = 150kHz, VIN = 3.6VP-P fIN = 7.5kHz fIN = 15kHz fIN = 50kHz fIN = 150kHz fIN = 450kHz Matching of Filter Gain External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 15kHz, Lowpass Filter Cutoff = 150kHz fIN = 15kHz fIN = 50kHz fIN = 150kHz External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 15kHz, Lowpass Filter Cutoff = 150kHz fIN = 16.5kHz fIN = 125kHz External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 15kHz, Lowpass Filter Cutoff = 150kHz fIN = 16.5kHz fIN = 125kHz
l l l l l
-1.6 0.4 -2.3
-32 -1.2 0.7 -1.9 -44
-30 -0.8 0.9 -1.3 -43
dB dB dB dB dB
l l l
0.2 0.2 0.2
dB dB dB
Filter Phase Either Channel
l l
137 -142
142 -138
146 -134
deg deg
Matching of Filter Phase
l l
2 1
deg deg
Filter Gain Either Channel External Clock = 90MHz, Highpass Filter Cutoff = 90kHz, Gain = 0dB Lowpass Filter Cutoff = 900kHz, VIN = 3.6VP-P fIN = 45kHz fIN = 90kHz fIN = 300kHz fIN = 900kHz fIN = 2700kHz Matching of Filter Gain External Clock = 90MHz, Highpass Filter Cutoff = 90kHz, Lowpass Filter Cutoff = 900kHz, VIN = 3.6VP-P fIN = 90kHz fIN = 300kHz fIN = 900kHz
l l l l l
-1.8 -0.1 -2.1
-29 -1.2 0.6 -1.1 -45
-27 -0.7 1.2 -0.5 -44
dB dB dB dB dB
l l l
0.3 0.6 0.4
dB dB dB
Filter Phase Either Chanel External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 90kHz, Lowpass Filter Cutoff = 900kHz fIN = 100kHz fIN = 750kHz Matching of Filter Phase External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 90kHz, Lowpass Filter Cutoff = 900kHz fIN = 100kHz fIN = 750kHz CLKCNTL = 3V (Note 4) RBIAS = 200k, Output Clock = 24.705MHz RBIAS = 54.9k, Output Clock = 90MHz
l l
136 -136
141 -131
145 -127
deg deg
l l l l
2 1.5 3 3
deg deg % %
Filter Cutoff Accuracy when Self Clocked
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LTC6602 ELECTRICAL CHARACTERISTICS
PARAMETER PGA Gain CONDITIONS Lowpass Cutoff = 150kHz, Highpass Filter Bypassed, Measured at DC, 0.6V to 2.4V Each Output Gain Setting = 0dB Gain Setting = 12dB Gain Setting = 24dB Gain Setting = 30dB Lowpass Cutoff = 150kHz, Highpass Filter Bypassed, Measured at DC, 0.6V to 2.4V Each Output Gain Setting = 0dB Gain Setting = 12dB Gain Setting = 24dB Gain Setting = 30dB Voltage Noise Referred to the Input Gain = 0dB Gain = 12dB Gain = 24dB Gain = 30dB Noise Bandwidth = 1.57MHz (Note 5), Referred to the Input Gain = 0dB Gain = 12dB Gain = 24dB Gain = 30dB VIN = 1.5VP-P, fIN = 100kHz Differential Common Mode Differential Offset Voltage at Either Output Differential Offset Voltage at Either Output HPF Bypassed, Lowest LPF Cutoff Differential Offset Voltage at Either Output HPF Bypassed, Highest LPF Cutoff Common Mode Offset Voltage VOCM = 1.5V, Supplies = 3V VOSCM = VOUT-CM - VOCM Common Mode Input from 0 to 3V V+IN = 3V Common Mode Input from 0 to 5V V+IN = 5V V+A = V+D = 3V, Pin 3 Open V+A = V+D = 3V, Pin 3 Open Lowpass Cutoff = 150kHz, Highpass Filter Bypassed, Measured at DC Source 1mA, VOUT High, Relative to V+A Sink 1mA, VOUT Low, Relative to GND Lowpass Cutoff = 150kHz, Highpass Filter Bypassed Sourcing Sinking Internal Clock (RBIAS = 54.9k); Sum of the Currents into V+D, V+A, and V+IN All Supplies Set to 3V HPF = 15k, LPF = 150k HPF = 45k, LPF = 300k HPF = 90k, LPF = 900k
l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted.
MIN TYP MAX UNITS
l l l l
0.4 11.6 23.5 29.1
0.8 12 23.8 29.6
1.2 12.4 24.1 30.1
dB dB dB dB
PGA Gain Matching
l l l l
0.2 0.2 0.3 0.3 -119 -131 -142 -146 -62 -74 -85 -89 -75 16 20 7 10 10 -40 20 15 30 30 70
dB dB dB dB dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm dBm dBm dBm dB k k mV mV mV mV
Noise At 200kHz
Integrated Noise
THD Input Impedance VOS Differential
VOSCM
CMR Differential VINCM /VOUTDIFF
l l l l
75 75 1.2 300
95 95 1.4 400 1.6 700
dB dB V
VOCM Pin Voltage VOCM Pin Input Impedance Output Swing
l l l l
200 200 4 10 15 25
500 500 25 50
mV mV mA mA
Short-Circuit Current
Supply Current
l l l
65 100 105
80 125 130
mA mA mA
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LTC6602 ELECTRICAL CHARACTERISTICS
PARAMETER Supply Current, Shutdown Mode Supply Voltage PSR RBIAS Resistor Range RBIAS Pin Voltage Clock Frequency Drift Over Temperature Clock Frequency Change Over Supply Output Clock Duty Cycle CLKIO Pin High Level Input Voltage CLKIO Pin Low Level Input Voltage CLKIO Pin Input Current CONDITIONS Sum of the Currents into V+D, V+A, and V+IN; All Supplies Set to 3V Shutdown Via Serial Interface, Control Bit D1 = 1. V+D, V+A Relative to GND V+IN Relative to GND V+D = V+A = V+IN, All from 2.7V to 3.6V V+D = V+A = 3.0V, V+IN from 4.5V to 5.5V Clock Frequency Error 3%, CLKCNTL = 3V 54.9k < RBIAS < 200k RBIAS = 54.9k, CLKCNTL Pin Open V+A, V+D from 2.7V to 3.6V, RBIAS = 54.9k, CLKCNTL Pin Open RBIAS = 54.9k CLKCNTL = 0V (Note 6) CLKCNTL = 0V (Note 6) CLKCNTL = 0V CLKIO = 0V (Note 7) CLKIO = V+D V+A = V+D = 3V, CLKCNTL = 3V IOH = -1mA IOH = -4mA V+A = V+D = 3V, CLKCNTL = 3V IOL = 1mA IOL = 4mA V+A = V+D = CLKCNTL = 3V, 20%/80%, CLOAD = 5pF V+A = V+D = CLKCNTL = 3V, 20%/80%, CLOAD = 5pF Pins 17, 20 Pins 17, 20 Pin 17 or Pin 20 = 0V (Note 7) Pin 17 or Pin 20 = V+D Pin 5 Pin 5 CLKCNTL = 0V (Note 7) CLKCNTL = V+D
l l l l l l l l l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted.
MIN TYP 170 2.7 2.7 50 80 54.9 1.17 40 -0.6 25 V+D - 0.3 0.3 0.1 50 0.6 75 60 95 200 MAX 235 3.6 5.5 UNITS A V V dB dB k V ppm/C %/V % V V
l l
-1 10 2.95 2.9 0.05 0.1 0.3 0.3 V+D - 0.3 0.3 -10 2 V+D - 0.5 0.5 -25 -15 15
A A V V V V ns ns V V A A V V A A
CLKIO Pin High Level Output Voltage CLKIO Pin Low Level Output Voltage CLKIO Rise Time CLKIO Fall Time SER, MUTE High Level Input Voltage SER, MUTE Low Level Input Voltage SER, MUTE Input Current CLKCNTL High Level Input Voltage CLKCNTL Low Level Input Voltage CLKCNTL Input Current
25
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LTC6602 ELECTRICAL CHARACTERISTICS
Pin Programmable Control Mode Specifications
SYMBOL V+D = 2.7V to 3.6V VIH VIL IIN Digital Input High Voltage Digital Input Low Voltage Digital Input Current Pins 6, 9-11, 21, 22 Pins 6, 9-11, 21, 22 Pins 6, 9-11, 21, 22 (Note 7)
l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Specifications apply to pins 6, 9-11, 21 and 22.
PARAMETER CONDITIONS MIN 2 0.8 -1 1 TYP MAX UNITS V V A
Serial Port DC and Timing Specifications
SYMBOL V+D = 2.7V to 3.6V VIH VIL IIN VOH VOL t1 t2 t3 t4 t5 t6 t7 t8 t9 Digital Input High Voltage Digital Input Low Voltage Digital Input Current Digital Output High Voltage Digital Output Low Voltage SDI Valid to SCLK Setup SDI Valid to SCLK Hold SCLK Low SCLK High CS Pulse Width LSB SCLK to CS CS Low to SCLK SDO Output Delay SCLK Low to CS Low (Note 6) (Note 6) CL = 15pF (Note 6) Pins 6, 9, 10 Pins 6, 9, 10 Pins 6, 9, 10 (Note 7) Pins 11, 21 Sourcing 500A Pins 11, 21 Sinking 500A (Note 6) (Note 6)
l l l l l l l l l l l l l l
PARAMETER
CONDITIONS
MIN 2
TYP
MAX
UNITS V
0.8 -1 VSUPPLY -0.3 0.3 60 0 100 100 60 60 30 125 0 1
V A V V ns ns ns ns ns ns ns ns ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: LTC6602C and LTC6602I are guaranteed functional over the operating temperature range of -40C to 85C. Note 3: LTC6602C is guaranteed to meet specified performance from 0C to 70C. The LTC6602C is designed, characterized and expected to meet specified performance from -40C to 85C but is not tested or QA sampled at these temperatures. The LTC6602I is guaranteed to meet the specified performance limits from -40C to 85C.
Note 4: This test measures the internal oscillator accuracy (deviation from the fCLK equation). Variations in the internal oscillator frequency cause variations in the filter cutoff frequency. See the "Applications Information" section. Note 5: 1.57MHz is the equivalent noise bandwidth of a 1MHz 1st order RC lowpass filter. Note 6: Guaranteed by design, not subject to test. Note 7: To conform to the Logic IC standard, current out of a pin is arbitrarily given a negative value.
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LTC6602 TYPICAL PERFORMANCE CHARACTERISTICS
Gain vs Frequency
20 10 TA = 25C VS = 3V EXTERNAL CLOCK RBIAS = 54.9k 0 GAIN = 0dB -70 15kHz-150kHz BPF 90kHz-900kHz BPF DISTORTION (dBc)
Distortion vs Input Frequency
TA = 25C, VS = 3V, DIFFERENTIAL INPUT, , VIN = 1.5VP-P, 12.4-82.4kHz BPF RBIAS = 200k 45kHz-300kHz BPF RBIAS = 54.9k, GAIN = 0dB , DISTORTION (dBc) HD3 12kHz-82kHz BPF HD2 45kHz-300kHz BPF -30
Distortion vs Output Voltage
TA = 25C V = 3V -40 f S = 100kHz IN DIFFERENTIAL INPUT -50 RBIAS = 54.9k RBIAS = 45kHz-300kHz BPF -60 GAIN = 0dB -70 -80 -90 -100 HD2 HD3
-75
GAIN (dB)
-10 -20 -30 -40 -50 45kHz-300kHz BPF -60 1k 10k 100k 1M FREQUENCY (Hz) 10M
6602 G01
-80
-85 HD2 12kHz-82kHz BPF -90 HD3 45kHz-300kHz BPF 300
66062 G02
0
50
100 150 200 250 INPUT FREQUENCY (kHz)
0
1
2 3 4 OUTPUT VOLTAGE (VP-P)
5
6
66062 G03
Distortion vs Gain
-70 TA = 25C VS = 3V fIN = 100kHz DIFFERENTIAL INPUT, VOUT = 1.5VP-P -75 R BIAS = 54.9k 45kHz-300kHz BPF -80 HD3 HD2 -85 -70
Distortion vs Highpass Cutoff Frequency
TA = 25C VS = 3V fIN = 100kHz DIFFERENTIAL INPUT, VIN = 1.5VP-P RBIAS = 54.9k fLP = 300kHz GAIN = 0dB HD3 HD2 -85 -70
Distortion vs Lowpass Cutoff Frequency
-75 DISTORTION (dBc)
-75 DISTORTION (dBc) HD3 -80 TA = 25C VS = 3V fIN = 100kHz DIFFERENTIAL INPUT, VIN = 1.5VP-P RBIAS = 54.9k fHP = 45kHz GAIN = 0dB 0 150 300 450 600 750 LOWPASS CUTOFF FREQUENCY (kHz) 900
6602 G06
DISTORTION (dBc)
-80
HD2
-85
-90
0
6
12 18 GAIN (dB)
24
30
6602 G04
-90
0
15 30 45 60 75 HIGHPASS CUTOFF FREQUENCY (kHz)
90
6602 G05
-90
Filter Cutoff Accuracy vs Supply Voltage
FILTER CUTOFF FREQUENCY DEVIATION (%) FILTER CUTOFF FREQUENCY DEVIATION (%) 0.10 RBIAS = 54.9k 45kHz-300kHz BPF GAIN = 0dB 0.4
Filter Cutoff Accuracy vs Temperature
COMMON MODE REJECTION (dB) VS = 3V 0.3 RBIAS = 54.9k 45kHz-300kHz BPF GAIN = 0dB 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -40 -20 0 20 40 60 TEMPERATURE (C) 80
6602 G08
Common Mode Rejection
120 110 100 90 80 70 60 GAIN = 0dB GAIN = 12dB CMR = VIN-CM /VOUT-DIFF
0.05
-40C
5 TYPICAL UNITS
0.00
25C
85C
-0.05 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
6602 G07
TA = 25C 50 V = 3V S GAIN = 24dB 40 VIN-CM = 0V GAIN = 30dB VIN-CM = 1.25VP-P 30 RBIAS = 54.9k 45kHz-300kHz BPF 20 1k 10k 100k 1M 10M FREQUENCY (Hz)
6602 G09
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LTC6602 TYPICAL PERFORMANCE CHARACTERISTICS
Common Mode Rejection
120 110 COMMON MODE REJECTION (dB) 100 90 80 GAIN = 12dB GAIN = 0dB CMR = VIN-CM /VOUT-DIFF COMMON MODE REJECTION (dB) 120
Common Mode Rejection
TA = 25C, VS = 3V, 110 VIN-CM = 0V, VIN-CM = 1.25VP-P , RBIAS = 54.9k, 90kHz-900kHz BPF 100 90 80 70 60 50 40 30 1M
6602 G10
Common Mode Rejection Ratio
120 110 100 90 CMRR (dB) 80 70 60 50 40 GAIN = 0dB GAIN = 12dB GAIN = 30dB GAIN = 24dB
70 GAIN = 24dB GAIN = 30dB 60 TA = 25C 50 V = 3V S 40 VIN-CM = 0V VIN-CM = 1.25VP-P 30 RBIAS = 54.9k 15kHz-150kHz BPF 20 1k 10k 100k FREQUENCY (Hz)
GAIN = 0dB
GAIN = 24dB
GAIN = 12dB
CMR = VIN-CM /VOUT-DIFF 20 10k 100k 1M FREQUENCY (Hz)
GAIN = 30dB 10M
6602 G11
TA = 25C, VS = 3V, 30 VIN-CM = 0V, VIN-CM = 1.25VP-P , RBIAS = 54.9k, 45kHz-300kHz BPF 20 1k 10k 100k 1M FREQUENCY (Hz)
10M
6602 G12
Common Mode Rejection Ratio
120 110 100 90 CMRR (dB) 80 70 60 50 40 TA = 25C, VS = 3V, 30 VIN-CM = 0V, VIN-CM = 1.25VP-P , RBIAS = 54.9k, 15kHz-150kHz BPF 20 1k 10k 100k FREQUENCY (Hz) GAIN = 0dB GAIN = 12dB CMRR (dB) GAIN = 30dB GAIN = 24dB 120
Common Mode Rejection Ratio
TA = 25C 110 VS = 3V VIN-CM = 0V 100 V IN-CM = 1.25VP-P 90 RBIAS = 54.9k 90kHz-900kHz BPF 80 GAIN = 12dB 70 60 50 40 30 1M
6602 G13
OIP3 vs Average Signal Frequency, fC
48 TA = 25C VS = 3V f1 = fC -5kHz, f2 = fC +5kHz 46 V OUT = 6dBm PER TONE FOR 2-TONE TEST RBIAS = 54.9k 45kHz-300kHz BPF 44 GAIN = 24dB 42 GAIN = 0dB 40 GAIN = 30dB GAIN = 12dB
GAIN = 24dB
GAIN = 0dB
GAIN = 30dB
20 10k
OIP3 (dBm) 10M
6602 G14
100k 1M FREQUENCY (Hz)
38
0
50 100 150 200 250 300 350 CENTER SIGNAL FREQUENCY, fC (kHz)
6602 G15
OIP3 vs Average Signal Frequency, fC
48 GAIN = 12dB GAIN = 24dB OIP3 (dBm) 44 GAIN = 0dB TA = 25C VS = 3V f1 = fC -5kHz f2 = fC +5kHz VOUT = 6dBm PER TONE FOR 2-TONE TEST RBIAS = 54.9k 15kHz-150kHz BPF 0 20 40 60 80 100 120 140 160 CENTER SIGNAL FREQUENCY, fC (kHz)
6602 G16
OIP3 vs Average Signal Frequency, fC
GAIN = 30dB 48 TA = 25C, VS = 3V f1 = fC -10kHz, f2 = fC +10kHz VOUT = 6dBm PER TONE 46 FOR 2-TONE TEST RBIAS = 54.9k 90kHz-900kHz BPF 44 50
OIP3 vs Temperature
VS = 3V VOUT = 6dBm PER TONE FOR 2-TONE TEST 48 RBIAS = 54.9k GAIN = 30dB fIN = 95kHz, 105kHz 15kHz-150kHz BPF 46 fIN = 145kHz, 155kHz 45kHz-300kHz BPF
46
GAIN = 12dB
OIP3 (dBm)
OIP3 (dBm)
42
42 GAIN = 24dB 40 GAIN = 30dB GAIN = 0dB 38 0 100 200 300 400 500 600 700 800 900 1000 CENTER SIGNAL FREQUENCY, fC (kHz)
6602 G17
44
40
42
fIN = 590kHz, 610kHz 90kHz-900kHz BPF
38
40 -40-30-20-10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C)
6602 G18
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LTC6602 TYPICAL PERFORMANCE CHARACTERISTICS
Output Impedance vs Frequency
100 TA = 25C VS = 3V RBIAS = 54.9k SUPPLY CURRENT (mA) 110
Supply Current vs Supply Voltage
CLKCNTL PIN FLOATING RBIAS = 54.9k 45kHz-300kHz BPF GAIN = 0dB 85C 100 25C -40C 95 120
Supply Current vs Temperature
90kHz-900kHz BPF 100 SUPPLY CURRENT (mA) 80 15kHz-150kHz BPF 60 40 VS = 3V 20 CLKCNTL PIN FLOATING RBIAS = 54.9k GAIN = 0dB 0 -40-30-20-10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C)
6602 G21
OUTPUT IMPEDANCE ()
105
45kHz-300kHz BPF
10 15kHz-150kHz BPF 90kHz-900kHz BPF 1 900kHz LPF
45kHz-300kHz BPF 0.1 1k 10k 100k 1M FREQUENCY (Hz) 10M
6602 G19
90 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
6602 G20
Clock Output Operating at 90MHz
1.25
RBIAS Pin Voltage vs IRBIAS
TA = 25C VS = 3V
RBIAS PIN VOLTAGE (V)
1.20
1V/DIV 0V
1.15
1.10 2.5ns/DIV
6602 G22
0
5
10 15 IRBIAS (A)
20
25
6602 G23
Input Referred Noise Density
1000 VOLTAGE NOISE DENSITY (nV/Hz) VOLTAGE NOISE DENSITY (nV/Hz) GAIN = 0dB INTEGRATED NOISE = 186.5VRMS GAIN = 12dB INTEGRATED NOISE = 47.1VRMS 1000
Input Referred Noise Density
GAIN = 0dB INTEGRATED NOISE = 189VRMS 1000 VOLTAGE NOISE DENSITY (nV/Hz)
Input Referred Noise Density
GAIN = 0dB INTEGRATED NOISE = 304.2VRMS GAIN = 12dB INTEGRATED NOISE = 77.6VRMS
100
100
100
10 GAIN = 30dB INTEGRATED NOISE = 7.5VRMS 1k GAIN = 24dB INTEGRATED NOISE = 12.6VRMS 1M
6602 G24
10
GAIN = 24dB INTEGRATED NOISE = 12.5VRMS 1 1k 10k 100k FREQUENCY (Hz)
GAIN = 12dB INTEGRATED NOISE= 47.8VRMS
10
1
GAIN = 30dB INTEGRATED NOISE = 7.2VRMS 1M
6602 G25
10k 100k FREQUENCY (Hz)
1 10k
GAIN = 24dB INTEGRATED NOISE = 20.7VRMS GAIN = 30dB INTEGRATED NOISE = 17.5VRMS 100k 1M FREQUENCY (Hz) 10M
6602 G26
TA = 25C, VS = 3V, EXTERNAL CLOCK RBIAS = 54.9k, 45kHz-300kHz BPF INTEGRATED NOISE BW = 1.57MHz
TA = 25C, VS = 3V, EXTERNAL CLOCK RBIAS = 54.9k, 15kHz-150kHz BPF INTERNAL NOISE BW = 400kHz
TA = 25C, VS = 3V, EXTERNAL CLOCK RBIAS = 54.9k, 90kHz-900kHz BPF INTERNAL NOISE BW = 2.5MHz
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LTC6602 PIN FUNCTIONS
V+IN (Pin 1): Input Voltage Supply (2.7V V 5.5V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1F capacitor unless it is tied to V+A (Pin 2). The bypass should be as close as possible to the IC, but is not as critical as the bypassing of V+A and V+D (Pin16). V+A (Pin 2): Analog Voltage Supply (2.7V V 3.6V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1F capacitor. The bypass should be as close as possible to the IC. VOCM (Pin 3): Output common mode voltage reference. If floated, an internal resistive divider sets the voltage on this pin to half the supply voltage (typically 1.5V), maximizing the dynamic range of the filter. If this pin is floated, it must be bypassed with a quality 0.1F capacitor to ground. This pin has a typical input impedance of 400 and may be overdriven. Driving this pin to a voltage other than the default value will reduce the signal range the filter can handle before clipping. RBIAS (Pin 4): Oscillator Frequency-Setting Resistor Input. The value of the resistor connected between this pin and ground determines the frequency of the master oscillator, and sets the bias currents for the filter networks. The voltage on this pin is held by the LTC6602 to approximately 1.17V. For best performance, use a precision metal film resistor with a value between 54.9k and 200k and limit the capacitance on this pin to less than 10pF This resistor is . necessary even if an external clock is used. CLKCNTL (Pin 5): Clock Control Input. This three-state input selects the function of CLKIO (Pin 15). Tying the CLKCNTL pin to ground allows the CLKIO pin to be driven by an external clock (CLKIO is the master clock input). If the CLKCNTL pin is floated, the internal oscillator is enabled, but the master clock is not present at the CLKIO pin (CLKIO is a no-connect). If the CLKCNTL pin is tied to V+D (Pin 16), the internal oscillator is enabled and the master clock is present at the CLKIO pin (CLKIO is the master clock output). To detect a floating CLKCNTL pin, the LTC6602 attempts to pull the pin toward mid-supply. This is realized with two internal current sources, one tied to V+D and CLKCNTL and the other one tied to ground and CLKCNTL. Therefore, driving the CLKCNTL pin high requires sourcing approximately 15A. Likewise, driving the CLKCNTL pin low requires sinking 15A. When the CLKCNTL pin is floated, preferably it should be bypassed by a 1nF capacitor to ground or it should be surrounded by a ground shield to prevent excessive coupling from other PCB traces. LPF1(CS) (Pin 6): Logic Input. When in pin programmable control mode, this pin is the MSB of the lowpass cutoff frequency control code; in serial control mode, this pin is the chip select input (active low). +INB, -INB (Pins 7, 8): Channel B differential inputs. The input range and input resistance are described in the Applications Information section. Input voltages which exceed V+IN (Pin 1) should be avoided. LPF0(SCLK) (Pin 9): Logic Input. When in pin programmable control mode, this pin is the LSB of the lowpass cutoff frequency control code; in serial control mode, this pin is the clock of the serial interface. HPF1(SDI) (Pin 10): Logic Input. When in pin programmable control mode, this pin is the MSB of the highpass cutoff frequency control code; in serial control mode, this pin is the serial data input. HPF0(SDO) (Pin 11): Logic Input. When in pin programmable control mode, this pin is the LSB of the highpass cutoff frequency control code; in serial control mode, this pin is the serial data output. -OUTB, +OUTB (Pins 12, 13): Channel B differential filter outputs. These pins can drive 1k and/or 50pF loads. For larger capacitive loads, an external 100 series resistor is recommended for each output. The common mode voltage of the filter outputs is the same as the voltage at VOCM (Pin 3). GND (Pin 14): Ground. Connect to a ground plane for best performance.
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10
LTC6602 PIN FUNCTIONS
CLKIO (Pin 15): When CLKCNTL (Pin 5) is tied to ground, CLKIO is the master clock input. When CLKCNTL is floated, CLKIO is pulled to ground by a weak, 5A pulldown. When CLKCNTL is tied to V+D (Pin 16), CLKIO is the master clock output. When configured as a clock output, this pin can drive 1k and/or 5pF loads. Heavier loads may cause inaccuracies due to supply bounce at high frequencies. V+D (Pin 16): Digital Voltage Supply (2.7V V 3.6V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1F capacitor. The bypass should be as close as possible to the IC. SER (Pin 17): Interface Selection Input. When tied to V+D (Pin 16), the interface is in pin programmable control mode, i.e. the filter gain and cutoff frequencies are programmed by the GAIN1, GAIN0, HPF1, HPF0, LPF1 and LPF0 pin connections. When SER is tied to ground, the filter gain, the filter cutoff frequencies and shutdown mode are programmed by the serial interface. -OUTA, +OUTA (Pins 18, 19): Channel A differential filter outputs. These pins can drive 1k and/or 50pF loads. For larger capacitive loads, an external 100 series resistor is recommended for each output. The common mode voltage of the filter outputs is the same as the voltage at VOCM (Pin 3). MUTE (Pin 20): MUTEX input. Drive to ground to disconnect and mute the inputs. Float or drive to V+D (Pin 16) for normal operation. GAIN0(D0) (Pin 21): Logic Input. When in pin programmable control mode, this pin is the LSB of the gain control code; in serial control mode, this pin is the LSB of the serial control register, an output. GAIN1 (Pin 22): Logic Input. When in pin programmable control mode, this pin is the MSB of the gain control code; in serial control mode, this pin is a no-connect. -INA, +INA (Pins 23, 24): Channel A differential inputs. The input range and input resistance are described in the Applications Information section. Input voltage levels can range from GND to the V+IN supply rail. Exposed Pad (Pin 25): Ground. The Exposed Pad must be soldered to PCB.
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11
LTC6602 BLOCK DIAGRAM
+INA 24 -INA 23 GAIN1 22 GAIN0(D0) 21 MUTE 20 +OUTA 19
V+IN 1
CHANNEL A
18 -OUTA
PGA V+A 2 CONTROL VDDA 1.6k VOCM 3 1.6k GND RBIAS 4 BIAS CLKCNTL 5 BIAS/OSC
LPF
HPF 17 SER BIAS CLK
16 V+D
CONTROL LOGIC
CLOCK GENERATOR 15 CLKIO
CONTROL
CLK 14 GND
PGA
LPF
HPF
LPF1(CS) 6
CHANNEL B
13 +OUTB
7 +INB
8 -INB
9 LPF0(SCLK)
10 HPF1(SDI)
11 HPF0(SDO)
12 -OUTB
6602 BD
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LTC6602 TIMING DIAGRAM
Timing Diagram of the Serial Interface
t1 t2 SCLK t9 t4 t3 t6 t7
SDI
D3
D2
D1
D0
D7 * * * * D4
D3
t5 CS t8 D4 PREVIOUS BYTE D3 D2 D1 D0 D7 * * * * D4 CURRENT BYTE D3
6602 TD
SDO
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13
LTC6602 APPLICATIONS INFORMATION
Theory of Operation (Refer to Block Diagram) The LTC6602 features two matched filter channels, each containing gain control, lowpass, and highpass networks that are controlled by a single control block and clocked by a single clock generator. The gain, lowpass and highpass sections can be independently programmed. The two channels are not independent, i.e. if the gain is set to 24dB, then both channels have a gain of 24dB. The filter can also be programmed to bypass the highpass filter networks, giving a lowpass response. The filter can be clocked with an external clock source, or using the internal oscillator. A resistor connected to the RBIAS pin sets the bias currents for the filter networks and the internal oscillator frequency (unless driven by an external clock). Altering the clock frequency changes the filter bandwidths. This allows the filters to be "tuned" to many different bandwidths. Pin Programmable Interface As shown in Figure 1, connecting SER to V+D allows the filter to be directly controlled through the pin programmable control lines GAIN1, GAIN0, HPF1, HPF0, LPF1 and LPF0. The HPF0(SDO) and GAIN0(D0) pins are bidirectional (inputs in pin programmable control mode, outputs in serial mode). In pin programmable control mode, the voltages at HPF0(SDO) and GAIN0(D0) cannot exceed V+D; otherwise, large currents can be injected to V+D through the internal diodes (see Figure 2). Connecting a 10k resistor at the HPF0(SDO) and GAIN0(D0) pins (see Figure 1) is recommended for current limiting, to less than 10mA. SER has an internal pull-up to V+D. None of the logic inputs have an internal pull-up or pull-down.
3.3V LTC6602 V+IN V+A V+D
3.3V LTC6602 V+IN V+A V+D +OUTA -OUTA
0.1F
0.1F
+ -
VIN
+INA -INA SER LPF1(CS) LPF0(SCLK) HPF1(SDI) HPF0(SDO) GAIN1 GAIN0(D0) GND
+
VOUT
+ -
LPF1 LPF0 HPF1 P HPF0 GAIN1 GAIN0 10k 10k VIN
+INA -INA SER LPF1(CS) LPF0(SCLK) HPF1(SDI) HPF0(SDO) GAIN1 GAIN0(D0) GND
+OUTA -OUTA
+
VOUT
-
-
LOWPASS CUTOFF = 900kHz (fCLK = 90MHz) HIGHPASS CUTOFF = 90kHz (fCLK = 90MHz) GAIN = 16
GAIN, BANDWIDTHS ARE SET BY MICROPROCESSOR. 10k RESISTORS ON HPF0(SDO) AND GAIN0(D0) PROTECT THE DEVICE IF VHPF0 > V+D OR VGAIN0 > V+D 6602 F01
Figure 1. Filter in Pin Programmable Control Mode
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14
LTC6602 APPLICATIONS INFORMATION
V+D SHUTDOWN OUT 6-BIT GAIN, BW CONTROL CODE
CS HPF0(SDO)
8-BIT LATCH
DIN
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 8-BIT SHIFT-REGISTER
(INTERNAL NODE)
6602 F02
SCLK
SDO
6602 F03
Figure 2. Bidirectional Design of HPFO(SDO) and GAIN0(D0) Pins
3.3V LTC6602 #1
Figure 3. Diagram of Serial Interface (MSB First Out)
3.3V LTC6602 #2
0.1F
V+IN V+A V+D
0.1F
V+IN V+A V+D
+
VIN1
+INA -INA SER
+OUTA -OUTA
+ -
VOUT1
+
VIN2
+INA -INA SER LPF1(CS)
+OUTA -OUTA
+ -
VOUT2
-
-
LPF1(CS) LPF1(CS) P SCLK LPF0(SCLK) SDI HPF1(SDI) GND GAIN0(D0) HPF0(SDO) OUT1 GAIN0(D0) HPF0(SDO) OUT2 SDO
LPF0(SCLK) HPF1(SDI) GND
SCLK
SDI
D15
D11
D10
D9
D8
D7
D3
D2
D1
D0
GAIN, BW CONTROL WORD FOR #2 SHUTDOWN FOR #2 CS
GAIN, BW CONTROL WORD FOR #1 SHUTDOWN FOR #1
6602 F04
Figure 4. Two Filters in a Daisy Chain Serial Control Register Definition
D7 GAIN0 D6 GAIN1 D5 LPF0 D4 LPF1 D3 HPF0 D2 HPF1 D1 SHDN D0 OUT
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LTC6602 APPLICATIONS INFORMATION
Serial Interface Connecting SER to ground allows the filter to be controlled through the SPI serial interface. When CS is low, the serial data on SDI is shifted into an 8-bit shift-register on the rising edge of the clock (SCLK), with the MSB transferred first (see Figure 3). Serial data on SDO is shifted out on the clock's falling edge. A high CS will load the 8 bits of the shift-register into an 8-bit D-latch, which is the serial control register. The clock is disabled internally when CS is pulled high. Note: SCLK must be low before CS is pulled low to avoid an extra internal clock pulse. SDO is always active in serial mode (never tri-stated) and cannot be "wire-or'ed" to other SPI outputs. In addition, SDO is not forced to zero when CS is pulled high. An LTC6602 may be daisy chained with other LTC6602s or other devices having serial interfaces. Daisy chaining is accomplished by connecting the SDO of the lead chip to the SDI of the next chip, while SCLK and CS remain common to all chips in the daisy chain. The serial data is clocked to all the chips then the CS signal is pulled high to update all of them simultaneously. Figure 4 shows an example of two LTC6602s in a daisy chained SPI configuration. GAIN1 and GAIN0 are the gain control bits (register bits D6 and D7 when in serial mode). Their function is shown in Table 1. In serial mode, register bit D1 can be set to `1' to put the device into a low power shutdown mode. Register bit D0 is a general purpose output (Pin 21) when in serial mode.
Table 1. Gain Control
GAIN 1 0 0 1 1 GAIN 0 0 1 0 1 PASSBAND GAIN (dB) 0 12 24 30
Self-Clocking Operation The LTC6602 features a unique internal oscillator which sets the filter cutoff frequency using a single external resistor connected to the RBIAS pin. The clock frequency is determined by the following simple formula (see Figure 5): fCLK = 494.1MHz * 10k/RBIAS Note: RBIAS 200k.
200 175 150 RBIAS (k) 125 100 75 50
20
30 40 50 60 70 80 DESIRED CLOCK FREQUENCY (MHz)
90
6602 F05
Figure 5. RBIAS vs Desired Clock Frequency
The design is optimized for V+A, V+D = 3V, fCLK = 90MHz, where the filter cutoff frequency error is typically <3% when a 0.1% external 54.9k resistor is used. With different resistor values and cutoff frequency control settings (HPF1, HPF0, LPF1 and LPF0), the highpass and lowpass cutoff frequencies can be accurately varied from 4.1175kHz to 90kHz and from 41.175kHz to 900kHz, respectively. Table 2 summarizes the cutoff frequencies that can be obtained with an external resistor (RBIAS) value of 54.9k. Note that the cutoff frequencies scale with the clock frequency. For example, if HPF1, HPF0, LPF1 and LPF0 are all equal to zero, and RBIAS is increased from 54.9k to 200k, fCLK will decrease from 90MHz to 24.705MHz, the lowpass cutoff frequency will be reduced from 150kHz to 41.175kHz, and the highpass cutoff frequency will be reduced from 15kHz to 4.1175Hz. The cutoff frequencies that can be obtained with an external resistor value of 200k
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LTC6602 APPLICATIONS INFORMATION
are shown in Table 3. When the LTC6602 is programmed for the lowest lowpass cutoff frequency (LPF1, LPF0 = `0'), the power is automatically reduced by about 35%.
Table 2. Cutoff Frequency Control, RBIAS = 54.9k, fCLK = 90MHz
LPF1 0 0 1 1 LPF0 0 1 0 1 Lowpass BW (kHz) 150 300 900 900 HPF1 0 0 1 1 HPF0 0 1 0 1 Highpass BW (kHz) 15 45 90 Bypass HPF
Table 3. Cutoff Frequency Control, RBIAS = 200k, fCLK = 24.705MHz
LPF1 0 0 1 1 LPF0 0 1 0 1 Lowpass BW (kHz) 41.175 82.35 247.05 247.05 HPF1 0 0 1 1 HPF0 0 1 0 1 Highpass BW (kHz) 4.1175 12.3525 24.705 Bypass HPF
The following graphs show a few of the possible combinations of highpass and lowpass filters.
Gain and Group Delay vs Frequency (45kHz to 300kHz Bandpass Response)
40 TA = 25C 30 VS = 3V EXTERNAL 20 CLOCK 10 RBIAS = 54.9k GAIN (dB) 0 -10 -20 -30 -40 -50 -60 1k 10k GROUP DELAY 100k 1M FREQUENCY (Hz) 20 GAIN = 30dB GAIN = 24dB 18 GAIN = 12dB GAIN = 0dB 16 14 12 10 8 6 4 2 0 10M
6602 G28
Gain and Group Delay vs Frequency (15kHz to 150kHz Bandpass Response)
40 TA = 25C 30 VS = 3V EXTERNAL 20 CLOCK 10 RBIAS = 54.9k GAIN (dB) 0 -10 -20 -30 -40 -50 -60 1k GROUP DELAY 10k 100k FREQUENCY (Hz) 60 GAIN = 30dB GAIN = 24dB GAIN = 12dB GAIN = 0dB 54 48 42 36 30 24 18 12 6 0 1M
6602 G29
GROUP DELAY (s)
GROUP DELAY (s)
Gain and Group Delay vs Frequency (90kHz to 900kHz Bandpass Response)
40 30 20 10 GAIN (dB) 0 -10 -20 -30 -40 -50 -60 10k GROUP DELAY 100k 1M FREQUENCY (Hz) GAIN = 30dB GAIN = 24dB GAIN = 12dB GAIN = 0dB 10 TA = 25C VS = 3V 9 EXTERNAL CLOCK 8 RBIAS = 54.9k 7 6 5 4 3 2 1 0 10M
6602 G30
Gain and Group Delay vs Frequency (900kHz Lowpass Response)
40 30 20 10 GAIN (dB) 0 -10 -20 -30 TA = 25C VS = 3V -50 EXTERNAL CLOCK RBIAS = 54.9k -60 1k 10k 100k 1M FREQUENCY (Hz) -40 GROUP DELAY (s) GAIN = 30dB GAIN = 24dB GAIN = 12dB GAIN = 0dB GROUP DELAY 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 10M
6602 G28
GROUP DELAY (s)
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LTC6602 APPLICATIONS INFORMATION
Preserving Oscillator Accuracy The oscillator is sensitive to transients on the positive supply. The IC should be soldered to the PC board and the PCB layout should include a 0.1F ceramic capacitor between V+A (Pin 2) and ground, as close as possible to the IC to minimize inductance. The PCB layout should also include an additional 0.1F ceramic capacitor between V+D (Pin 16) and ground. Avoid parasitic capacitance on RBIAS (Pin 4) and avoid routing noisy signals near RBIAS. Use a ground plane connected to Pin 14 and the Exposed Pad (Pin 25). Alternative Methods of Setting the Clock Frequency of the LTC6602 The oscillator may be programmed by any method that sinks a current out of the RBIAS pin. The circuit in Figure 6 sets the clock frequency by using a programmable current source and in the expression for fCLK, the resistor RBIAS is replaced by the ratio of 1.17V/ICONTROL. Because the voltage of the RBIAS pin is approximately 1.17V 5%, the Figure 6 circuit is less accurate than if a resistor controls the clock frequency. Figure 7 shows the LTC6602's oscillator configured as a VCO. A voltage source is connected in series with the RBIAS resistor. The clock frequency, fCLK, will vary with VCONTROL. Again, this circuit decouples the relationship between the current out of the RBIAS pin and the voltage of the RBIAS pin; the frequency accuracy will be degraded. The clock frequency, however, will increase monotonically with decreasing VCONTROL. Operation Using an External Clock The LTC6602 may be clocked by an external oscillator for tighter bandwidth control by pulling CLKCNTL (Pin 5) to ground and driving a clock into CLKIO (Pin 15). If an external clock is used, the RBIAS resistor is still necessary. The value of RBIAS must be no larger than the value that would be required for using the internal oscillator. For example, a 100k resistor would program the internal oscillator for 49.41MHz, so an external oscillator frequency of 49.41MHz would require an RBIAS resistance of no more than 100k. If the value of RBIAS is too large, the filters will not receive a large enough bias current, possibly causing errors due to insufficient settling.
RBIAS RBIAS RBIAS ICONTROL VCONTROL
+ -
fCLK = 10k * (494.1MHz/1.17V) * ICONTROL(A)
6602 F06
fCLK = 494.1MHz * (10k/RBIAS) * (1 - VCONTROL/1.17V)
6602 F07
Figure 6. Current Controlled Clock Frequency
Figure 7. Voltage Controlled Clock Frequency
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LTC6602 APPLICATIONS INFORMATION
-70 TA = 25C fIN = 100kHz DIFFERENTIAL INPUT, VIN = 1.5VP-P -75 RBIAS = 54.9k 45kHz-300kHz BPF GAIN = 0dB -80 HD3 HD2 -85 -70 TA = 25C fIN = 100kHz DIFFERENTIAL INPUT, VIN = 1.5VP-P -75 RBIAS = 54.9k 45kHz-300kHz BPF GAIN = 0dB HD3 -80 HD2 -85
DISTORTION (dBc)
-90
DISTORTION (dBc) 3.0
6602 F08
0
0.5 1.0 1.5 2.0 2.5 COMMON MODE INPUT VOLTAGE (V)
-90
0
1 2 3 4 COMMON MODE INPUT VOLTAGE (V)
5
6602 F09
Figure 8. Distortion vs Common Mode Input Voltage (3V)
Figure 9. Distortion vs Common Mode Input Voltage (5V)
Input Common Mode and Differential Voltage Range The input signal range extends from zero to the V+IN supply voltage. This input supply can be tied to V+A and V+D, or driven up to 5.5V for increased input common mode voltage range. Figures 8 and 9 show the distortion of the filter versus common mode input voltage with a 1.5VP-P differential input signal. For best performance, the inputs should be driven differentially. For single ended signals, connect the unused input to VOCM (Pin 3) or to a quiet DC reference voltage. To achieve the best distortion performance, the input signal should be centered around the DC voltage of the unused input. Refer to the Typical Performance Characteristics section to estimate the distortion for a given input level. Dynamic Input Impedance The unique input sampling structure of the LTC6602 has a dynamic input impedance which depends on the configuration and the clock frequency. This dynamic input impedance has both a differential component and a common mode component. The common mode input impedance is a function of the clock frequency and the control bit LPF1. The differential input impedance is a function of the clock frequency and the control bits LPF1, GAIN1 and GAIN0. Table 4 shows the typical input impedances for a clock frequency of 90MHz. These input impedances are all proportional to 1/fCLK, so if the clock frequency were reduced
by half to 45MHz, the impedances would be doubled. The typical part to part variation in dynamic input impedance for a given clock frequency is -20% to +35%.
Table 4. Differential, Common Mode Input Impedances, fCLK = 90MHz
GAIN1 0 0 0 0 1 1 1 1 GAIN0 0 0 1 1 0 0 1 1 LPF1 0 1 0 1 0 1 0 1 Differential Input Impedance (k) 16 6 8 2.8 2.6 1.8 2.4 1.3 Common Mode Input Impedance (k) 20 6.7 20 6.7 20 6.7 20 6.7
Output Common Mode and Differential Voltage Range The output voltage is a fully differential signal with a common mode level equal to the voltage at VOCM. Any of the filter outputs may be used as single-ended outputs, although this will degrade the performance. The output voltage range is typically 0.5V to V+A - 0.5V (V+A = 2.7V to 3.6V). The common mode output voltage can be adjusted by overdriving the voltage present on VOCM. To maximize the undistorted peak-to-peak signal swing of the filter, the VOCM voltage should be set to V+A /2. Note that the
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LTC6602 APPLICATIONS INFORMATION
-20 -30 DISTORTION (dBc) -40 -50 -60 -70 -80 HD2 -90 0.5 HD3 TA = 25C fIN = 100kHz VIN = 1.5VP-P RBIAS = 54.9k 45kHz-300kHz BPF GAIN = 0dB 0.1F V+IN V+A V+D +INA -INA VIN+ +OUTA -OUTA VOUT+ VOUT- VSUPPLY LTC6602
+ -
VIN-
+ -
1F
VOCM GND
1.0 1.5 2.0 2.5 COMMON MODE OUTPUT VOLTAGE (V)
6602 F10
DC COUPLED INPUT VIN (COMMON MODE) = (VIN+ + VIN-)/2 VOUT (COMMON MODE) = (VOUT+ + VOUT-)/2 = VSUPPLY/2
6602 F11
Figure 10. Distortion vs Common Mode Output Voltage
VSUPPLY VSUPPLY LTC6602 V+IN V+A V+D +INA -INA VIN+ -OUTA -OUTB VIN+ 0.1F
Figure 11. DC Coupled Inputs
VSUPPLY VSUPPLY LTC6602 V+IN V+A V+D +INA -OUTA -OUTB
0.1F RPULL-UP 0.1F RPULL-UP
0.1F 1.87k 1.87k
+ -
VIN-
+ -
0.1F
1F
VOCM GND
6602 F12a
+ -
1.87k VIN-
-INA
+ -
0.1F
1.87k
1F
VOCM GND
6602 F12b
AC COUPLED INPUT VIN (COMMON MODE) = VSUPPLY/2
AC COUPLED INPUT =
RCM * VSUPPLY = COMMON MODE AT +INA AND -INA 2 * RCM + 1.87k
(a) Fixed Lowpass Cutoff Frequency
(b) Variable Lowpass Cutoff Frequency
Figure 12. AC Coupled Inputs
output common mode voltages of the two channels are not independent as they are both set by the VOCM pin. Figure 10 illustrates the distortion versus output common mode voltage for a 1.5VP-P differential input voltage and a common mode input voltage that is equal to mid-supply. Interfacing to the LTC6602 The input and output common mode voltages of the LTC6602 are independent. The input common mode voltage is set by the signal source if DC coupled, as shown in Figure 11. If the inputs are AC coupled, the input common mode voltage will pulled to ground by an equivalent resistance of RCM, shown in Table 4. This does not affect the filter's performance as long as the input amplitude is less than 0.5VP-P. At low filter gain settings, a larger input voltage swing may be desired. Figure 12 shows two circuits with AC coupled inputs. In a fixed lowpass cutoff
frequency, connecting resistors between each input and V+IN will pull the input common mode voltage up, increasing the input signal swing (Figure 12a). The resistance, RPULL-UP, necessary to set the input common mode voltage, VICM, to any desired level can be calculated by RPULL where RCM = 20k * 90MHz/fCLK for LPFI = 0 RCM = 6.7k * 90MHz/fCLK for LPFI = 1 For example, if the lowpass cutoff frequency is set to 300kHz, 20k resistors connected between each input and V+IN will set the input common mode voltage to mid-supply.
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UP = RCM
VSUPPLY VICM
1
20
LTC6602 APPLICATIONS INFORMATION
3.3V LTC6602 MASTER V+IN V+A V+D RBIAS RBIAS 3.3V LTC6602 SLAVE V+IN V+A V+D +OUTA -OUTA RBIAS RBIAS 0.1F 0.1F
+
VIN1
+INA -INA CLKCNTL CLKIO GND
+
VOUT1
+
VIN2
+INA -INA CLKCNTL CLKIO GND
+OUTA -OUTA
+
VOUT2
-
-
-
-
6602 F13
Figure 13. Two Filters in a Master/Slave Configuration
If the lowpass cutoff frequency varies then the Figure 12b circuit must be used. The output common mode voltage is equal to the voltage of the VOCM pin. The VOCM pin is biased to one half of the supply voltage by an internal resistive divider (see Block Diagram). To alter the common mode output voltage, VOCM can be driven with an external voltage source or resistor network. If external resistors are used, it is important to note that the internal 1.6k resistors can vary 30% (their ratio varies only 1%). The filter outputs can also be AC coupled. The LTC6602 can be interfaced to an A/D converter by pulling CLKCNTL (Pin 5) to V+D. This configures CLKIO (Pin 15) as a clock output, which can be used to drive the clock input of the A/D converter. This allows the A/D converter to be synchronized with the filter sampling clock, avoiding "beat frequencies" and simplifying the board layout. Any routing attached to the CLKIO pin should be as short as possible, in order to minimize ringing.
Similarly, two LTC6602s can be connected in a master/ slave configuration as shown in Figure 13. This results in four matched filter channels, all synchronized to the same clock. The master has its CLKCNTL pin pulled to V+D, configuring its CLKIO pin as an output, while the slave has its CLKCNTL pin pulled to ground, configuring its CLKIO pin as an input. Output Drive The filter outputs can drive 1k and/or 50pF loads connected to AC ground with a 0.5V to 2.5V signal (corresponding to a 4VP-P differential signal). For differential loads (loads connected between +OUTA and -OUTA or +OUTB and -OUTB) the outputs can produce a 4VP-P signal across 2k and/or 25pF For smaller signal amplitudes, the outputs can . drive correspondingly heavier loads. For larger capacitive loads, an external 50 series resistor is recommended for each output.
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21
LTC6602 APPLICATIONS INFORMATION
Mute Function The LTC6602 features a mute function which is asserted by pulling MUTE (Pin 20) to ground. This breaks the signal path that leads from the input pins to the filter networks, attenuating the input signal by at least 20dB. The mute function can be used to protect the filter inputs from large transients. The filter clock continues to run when the filter is muted, allowing for a fast recovery time when MUTE is de-asserted. Typically, the recovery time is less than 5s, as shown in Figure 14. When the mute function is asserted, the differential input impedance becomes very high, but the common mode input impedance to ground remains the same. This keeps the input common mode voltage stable when muted, even when the inputs are AC coupled. Connecting GAIN0(D0) to MUTE allows for serial control of the mute function. MUTE has an internal pull-up to V+D. A ground plane should be used. Noisy signals should be isolated from the filter input pins. The output DC offset typically changes less than 2mV when the clock frequency varies from 24.705MHz to 90MHz. The offset is measured by connecting the inputs to VOCM and measuring the differential voltage at the filter's output. Aliasing Aliasing is an inherent phenomenon of sampled data filters. Significant aliasing only occurs when the frequency of the input signal approaches the sampling frequency or multiples of the sampling frequency. The ratio of the LTC6602 input sampling frequency to the clock frequency, fCLK, is determined by the state of control bit LPF1. If LPF1 is set to `0', the input sampling frequency is equal to fCLK/3. If LPF1 is set to `1', the input sampling frequency is equal to fCLK. Input signals with frequencies near the input sampling frequency will be aliased to the passband of the filter and appear at the output unattenuated. A simple LC anti-aliasing filter is recommended at the filter inputs to attenuate frequencies near the input sampling frequency that will be aliased to the passband. For example, if the clock frequency is set to 90MHz and the lowpass cutoff frequency of the filter is set to it's maximum (LPF1 = `1'), the lowest frequency that would be aliased to the passband would be fCLK - fCUTOFF, i.e. 90MHz - 900kHz = 89.1MHz. In order to attenuate this frequency by 40dB, an LC filter with a cutoff frequency of 8.91MHz or lower would be required at the filter inputs. The capacitor connected between the LTC6602 filter inputs should be at least 150pF to provide sufficient charge to the input sampler. If there is no anti-aliasing filter, the LTC6602 filter inputs should be driven by a low impedance source (<100). Wideband Noise The wideband noise of the filter is the RMS value of the device's output noise spectral density. The wideband noise voltage is used to determine the operating signal-to-noise ratio at a given distortion level. The wideband noise is nearly independent of the value of the clock frequency and excludes the clock feedthrough. Most of the wideband noise is concentrated in the filter passband and cannot be removed with post filtering.
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MUTE (2V/DIV)
VOUT (1V/DIV)
4s/DIV
6602 F14
Figure 14. Mute Function Recovery Time
Clock Feedthrough Clock feedthrough is defined as the RMS value of the clock frequency and its harmonics that are present at the filter's output. The clock feedthrough is measured with +INA and -INA (or +INB, -INB) tied to VOCM and depends on the PC board layout and the power supply decoupling. The clock feedthrough can be reduced with a simple RC post filter. DC Offset The output DC offset of the LTC6602 is less than 15mV. To obtain optimum DC offset performance, appropriate PC board layout techniques should be used. The filter IC should be soldered to the PC board. The power supplies should be well decoupled including 0.1F ceramic capacitors from V+D (Pin 16) and V+A (Pin 2) to ground.
22
LTC6602 APPLICATIONS INFORMATION
100 120 TA = 25C VS = 3V 100 CLKCNTL PIN FLOATING HPF1 = 0 HPF0 = 1 80 GAIN = 0dB 60 40 20 0 10k LPF1 = 0 LPF0 = 0 LPF1 = 0 LPF0 = 1 LPF1 = 1
HPF1 = 0 HPF1 = 0 HPF0 = 0 HPF0 = 1
LPF1 = 1 LPF1 = 0 LPF0 = 1
10
HPF1 = 1 LPF1 = 0 HPF0 = 0 LPF0 = 0 1k 10k 100k FILTER CUTOFF FREQUENCY (Hz) 1M
6602 F15
SUPPLY CURRENT (mA)
fCLK (MHz)
100k LOWPASS CUTOFF FREQUENCY (Hz)
1M
6602 F16
Figure 15. fCLK vs Filter Cutoff Frequencies
Figure 16. Supply Current vs Lowpass Cutoff Frequency
Table 5. Total Input Referred Integrated Noise Voltage (Passband Gain = 30dB)
LPF1 0 0 1 LPF0 0 1 X HPF1 0 0 1 HPF0 0 1 0 Noise Voltage -90dBm -89dBm -82dBm
Power Supply Current The power supply current depends on the state of the lowpass cutoff frequency controls (LPF1, LPF0) and the value of RBIAS. When the LTC6602 is programmed for the lowest lowpass cutoff frequency (LPF1 = LPF0 = `0'), the supply current is reduced by about 35% relative to the supply current for the higher bandwidth settings. Power supply current vs. cutoff frequency for various bandwidth settings is shown in the "Typical Performance Characteristics" section. The LTC6602 can be programmed through the serial interface to enter into a low power shutdown mode as described in the Serial Interface section. The power supply current during shutdown is less than 235A. Supply Current versus Noise Tradeoff The passband of the LTC6602 is determined by the master clock frequency (which is set by RBIAS when the internal oscillator is used), HPF1, HPF0, LPF1 and LPF0. The LTC6602 is optimized for use with RBIAS having a value between 200k and 54.9k to set the internal oscillation
frequency from 24.705MHz to 90MHz. Both lowpass and highpass corner frequencies are proportional to the clock frequency (internal or external). To extend the filter's operational frequency range, the master clock is divided down before reaching the filter. LPF1 and LPF0 set the division ratio of the lowpass clock while HPF1 and HPF0 set the division ratio of the highpass clock. Figure 15 shows the possible cutoff frequencies versus fCLK, HPF1, HPF0, LPF1 and LPF0. Overlapping frequency ranges allow more than one possible choice of bandwidth settings for some cutoff frequencies. Figure 16 shows supply current as a function of the lowpass cutoff frequency, LPF1 and LPF0. Note that the higher bandwidth setting always gives the minimum supply current for a given cutoff frequency. The total integrated noise voltage for a passband gain of 30dB is shown in Table 5. Note that the noise is higher for the higher bandwidth settings. This creates a tradeoff between supply current and noise. For a given cutoff frequency, using the highest possible bandwidth setting gives the minimum supply current at the expense of higher noise.
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23
LTC6602 APPLICATIONS INFORMATION
The LTC6602, an Adaptable Baseband Filter for an RFID Reader A radio-frequency identification (RFID) system is an auto-id technology that identifies any object that contains a coded tag. An RFID system consists of a reader (or interrogator) and a tag. An RFID system capable of identifying multiple tags at a maximum operating distance operates in the UHF frequency range. A UHF reader transmits information to a tag by modulating an RF signal in the 860MHz to 960MHz frequency range. Typically a tag is passive, meaning that it receives all of its operating energy from a reader that transmits a continuous wave (CW) RF signal to power a tag. A tag responds by modulating the reflection coefficient of its antenna, thereby backscattering an information signal to the reader. Reliable detection of a tag signal requires communication protocols that define the physical and operating interaction between readers and tags. The latest UHF RFID protocol, the Electronic Product CodeTM (EPC) global class-1 generation 2 standard (C1G2), have been accepted worldwide and is also known as ISO 18000-6C. The C1G2 standard defines a reader to tag and a tag to reader communication using a flexible set of signal modulation, data encoding, data rates and command procedures. C1G2 specifies reader and tag data symbols using pulse-interval encoding. Tag signal detection requires measuring the time interval between signal transitions (a data "1" symbol has a longer interval than a data "0" symbol). The reader initiates a tag inventory by sending a signal that instructs a tag to set its backscatter data rate and encoding. C1G2 certified RFID readers can operate in an RF environment where many readers are in close proximity. The three operating modes of C1G2, single interrogator, multiple interrogator and dense interrogator, define the spectral limits of reader and tag signals for an optimum balance of reliable multitag detection and high data throughput (for more information on C1G2, consult the references at the end of this design note). The advantages of C1G2 complex protocols can be realized by using a reader whose receiver contains a high linearity direct conversion I and Q demodulator, a low noise amplifier, a dual baseband filter with variable gain and bandwidth and a dual analog to digital converter (ADC). Certified C1G2 UHF RFID readers can adapt to a great variety of operating conditions. To achieve operating flexibility a reader's baseband circuits must include an adaptable bandwidth filter. Figure 17 shows an LTC6602 based filter circuit that uses SPI control to vary the filter's bandwidth to adjust for the C1G2 complex set of data rates, encoding and modulation. The filter's clock frequency is set by the SPI control of 8-bit LTC2630 DAC (digital to analog converter). The DAC voltage through a resistive divider sets the current into the LTC6602 RBIAS pin. The resistive divider sets the clock frequency range for a DAC voltage range 0V to 3V. For the resistor values in Figure 17 (191k and 61.9k) the clock frequency range is 40MHz to 100MHz (234.4kHz per bit). The lowpass and highpass division ratio is set by the SPI control of the LTC6602. The cutoff range for the highpass filter is 6.7kHz to 100kHz and for the lowpass filter is 66.7kHz to 1MHz. The optimum filter bandwidth setting can be adjusted by a software algorithm and is a function of the reader's data clock, data rate, encoding and modulation. The filter bandwidth must be sufficiently narrow to maximize the dynamic range to the ADC input and wide enough to preserve signal transitions and pulse width. If the filter setting is optimum then a DSP algorithm can reliably detect tag data. Figure 18a shows the filter's time response to a typical tag symbol sequence (a "short" pulse interval followed by a "long" pulse interval). The lowpass cutoff frequency is set equal to the reciprocal of the shortest interval (fCUTOFF = 1/10s = 100kHz). If the lowpass cutoff frequency is lower the signal transition and time interval will be distorted beyond recognition by any tag signal detection algorithm. The setting of the highpass cutoff frequency is more qualitative than specific. The highpass cutoff frequency must be lower than the reciprocal of the longest interval (for Figure 18 example, highpass fCUTOFF < 1/20s < 50kHz) and as high as possible to decrease the receiver's low frequency noise (baseband amplifier and down-converted phase and amplitude noise). Figures 18a and 18b show the filter's total response (lowpass plus highpass filter). The filter's output is shown with 30kHz and a 10kHz highpass cutoff frequency setting. Comparing the filter outputs with a 10kHz and a 30kHz highpass setting, the signal transitions and time intervals of the 10kHz output are adequate for
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24
LTC6602 APPLICATIONS INFORMATION
detecting the symbol sequence (in an RFID environment, noise will be superimposed on the output signal). In general, increasing the lowpass fCUTOFF and/or decreasing the highpass fCUTOFF "enhances" signal transitions and intervals and increases filter output noise.
5V 0.1F
3V 0.1F
1 V+IN 24 +INA SPI CONTROL OF DAC SETS THE LTC6602 CLOCK FREQUENCY 40MHz TO 100MHz 1 2 3 CS SCLK SDI VOUT GND 6 5 174k 0.1F 68.1k 0.1F Q CHANNEL INPUT I CHANNEL INPUT 23 -INA 7 +INB 8 4 3 20 21 3V LTC2630 8-BIT DAC TRANSMITTER MUTE INPUT DAC VOUT RANGE 0V TO 2.5V (USING THE LTC2630 INTERNAL REFERENCE) 22 14 25
2 V+A
16 V+D -OUTA 18
4 V+
+OUTA 19 I CHANNEL OUTPUT -OUTB 12 Q CHANNEL OUTPUT LTC6602 +OUTB 13 -INB 15 CLKIO RBIAS 17 SER VOCM 5 3V CLKCNTL MUTE 11 GAIN0(D0) HPFO(SDO) 10 HPFI(SDI) GAIN1 SPI CONTROL OF LTC6602 9 SETS THE FILTER GAIN AND THE LPFO(SCLK) GND LOWPASS AND HIGHPASS 6 LPF1(CS) GND DIVISION RATIO ADC VCOM INPUT
CS1
SCK
SDI
CS2
6602 F17
Figure 17. An Adaptable RFID Baseband Filter with SPI Control
LOWPASS ONLY FILTER 100kHZ LOWPASS
100kHz LOWPASS + 30kHz HIGHPASS FILTER
100kHz LOWPASS + 10kHz HIGHPASS FILTER
TYPICAL TAG SYMBOL SEQUENCE
0 10 20 30 40 50 60 70 80 90 100110120 (s)
6602 F19a
0 10 20 30 40 50 60 70 80 90 100110120 (s)
6602 F19b
0 10 20 30 40 50 60 70 80 90 100110120 (s)
6602 F19c
(a)
(b) Figure 18. Filter Transient Response to a Tag Symbol Sequence
(c)
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25
LTC6602 TYPICAL APPLICATIONS
Switching the RBIAS Resistor
PARALLEL CONTROL 1 V+IN 24 +INA 23 -INA 7 +INB 8 4 R3 SOT-363 R2 R1 0.1F 3 20 21 22 14 25 DIODES INC DMN2004DMK CLK1 CLK0 0 0 RBIAS1 0 1 RBIAS2 1 0 RBIAS3 1 1 RBIAS4 RBIAS1 > RBIAS2 OR RBIAS3 RBIAS = 4941 fCLK RBIAS1 IN k fCLK IN MHz R1 = RBIAS1 -INB RBIAS VOCM MUTE 2 V+A 3V 16 V+D -OUTA 18 +OUTA 19 -OUTB 12 LTC6602 +OUTB 13 CLKIO SER CLKCNTL 15 17 5 11 10 9 6 VOCM MUTE 3V 0.1F
GAIN0(D0) HPF0(SDO) GAIN1 GND GND HPF1(SDI) LPF0(SCLK) LPF1(CS)
fCLK1 fCLK2 fCLK3 fCLK4
CLK1
CLK0
GAIN1 GAIN0
LPF1
LPF0
HPF1
HPF0
DESIGN PROCEDURE 1. CHOOSE fCLK1, fCLK2 AND fCLK3 2. CALCULALTE RBIAS1, RBIAS2 AND RBIAS3 3. CALCULATE R2, R3 AND RBIAS4 R2 = RBIAS1 * RBIAS2 RBIAS1 - RBIAS2 R3 = RBIAS1 * RBIAS3 RBIAS1 - RBIAS3 RBIAS4 = R1 * R2 * R3 R1 * (R2 + R3) + R2 * R3 3V 1 V+IN 24 +INA 2 V+A 16 V+D -OUTA 18 +OUTA 19 -OUTB 12 LTC6602 +OUTB 13 CLKIO SER CLKCNTL 15 17 5 11 10 9 6 VOCM MUTE 3V 0.1F
SERIAL CONTROL
DAC VOUT RANGE, 0V TO 2.5V (USING LTC2630 INTERNAL REFERENCE) 1 2 3 CS SCLK SDI LTC2630 8-BIT DAC DAC VOUT 0V 2.5V VOUT GND V+ 6 5 4 R2 0.1F R1 0.1F
23 -INA 7 +INB 8 4 3 20 21 -INB RBIAS VOCM MUTE
GAIN0(D0) HPF0(SDO) GAIN1 GND GND HPF1(SDI) LPF0(SCLK) LPF1(CS)
3V LTC6602 fCLK fCLKHI fCLKLO
22 14 25
R1 =
1.056 * 1013 1.137 * fCLKHI + fCLKLO
R2 = 1.056 * 1013 fCLKHI - fCLKLO
CS1
SCLK
SDI
CS2
SDO
6602 TA02
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26
LTC6602 PACKAGE DESCRIPTION
UF Package 24-Lead Plastic QFN (4mm x 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 0.05
4.50
0.05 3.10
2.45 0.05 0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW--EXPOSED PAD 0.75 0.05 R = 0.115 TYP PIN 1 NOTCH R = 0.20 TYP OR 0.35 45 CHAMFER
4.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6)
23 24 0.40 1 2 0.10
2.45 0.10 (4-SIDES)
(UF24) QFN 0105
0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)--TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25
0.05
0.50 BSC
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC6602 TYPICAL APPLICATION
Direct Conversion Demodulator and Programmable Baseband Filter
RF IN 4.7pF 270nH* 10pF 4321 GND GND RF GND 16 5 6 5V 1F 0.1F 1000pF GND LO GND VCC 17 9 10 11 12 270nH* 1000pF LO IN 4.7pF MUTE INPUT FROM TRANSMITTER 10pF EN VCC 15 LT5575 14 10pF 13 10pF 270nH* 10pF 270pF 10pF 0.1F 38.3k 10pF 270pF 270nH* 10pF 1 V+IN 24 +INA I INPUT 23 -INA Q INPUT 7 +INB 8 -INB 4 3 20 21 22 14 25 RBIAS VOCM MUTE 2 16 V+A V+D -OUTA 18 +OUTA 19 I OUTPUT -OUTB 12 LTC6602 +OUTB 13 CLKIO SER CLKCNTL 15 17 5 11 10 9 6 CS SCLK SDI SPI CONTROL INPUT
6602 TA03
5V 0.1F
3V 0.1F
7V CC 8 VCC
Q OUTPUT CLOCK INPUT
GAIN0(D0) HPF0(SDO) GAIN1 GND GND HPF1(SDI) LPF0(SCLK) LPF1(CS)
VOCM INPUT FROM ADC *COILCRAFT 0603HP-R27X
RELATED PARTS
PART NUMBER LTC1563 LTC1565-31 LTC1566-1 LT(R)1567 LT1568 LTC2291 LTC2296 LT5516 LT5575 LT66002.5/5/10/15/20 DESCRIPTION 4th Order Filter Building Block 7th Order, Fully Differential 650kHz Lowpass Filter 7th Order, Fully Differential 2.3MHz Lowpass Low Noise, Filter Building Block Up to 5MHz 4th Order Filter Building Block, Configurable as 2 Matched Lowpass, Bandpass or 4-Pole Lowpass Dual 12-Bit, 25 Msps A/D Converter Dual 14-Bit, 25 Msps A/D Converter 800MHz to 1.5GHz Direct Conversion I/Q Demodulator 800MHz to 2.7GHz Direct Conversoin I/Q Demodulator Fully Differential Amplifier and Lowpass Filter Cutoff Frequencies: 2.5MHz/5MHz/10MHz/20MHz COMMENTS Lowpass or Bandpass Filter, 256Hz to 256kHz No External Components, Low Offset, SO8 Pkg No External Components, Low Noise, SO8 Pkg Differential Rail-to-Rail Output, MSOP Pkg 200kHz fc 5MHz, Low Noise, Rail-to-Rail Input/Output, Programmable Gain, Shutdown Mode Low Power (150mW), Single 3V Supply; 71.4dB SNR, 90dB SFDR Low Power (150mW), Single 3V Supply; 74.5dB SNR, 90dB SFDR 21.5dBm IIP3; 12.8dB NF 28dBm IIP3 at 900MHz; 13.2dBm P1dB; Integrated RF Input Balance Transformer Programmable Gain, Adjustable Output CM Voltage, Specified for 3V, 5V, 5V
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28 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0908 REV A * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2008

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